1. Field of the Invention
The present invention relates to a sync chip clamping/sync separator circuit for use in a video equipment, such as a television receiver, a video tape recorder or the like.
2. Description of the Related Art
Heretofore, video equipment includes a video signal clamping circuit to hold a peak portion of a sync (synchronizing) signal at constant voltage level independently of brightness or amplitude of a video signal.
FIG. 1 of the accompanying drawings shows an arrangement of a sync chip clamping circuit which is such a video signal clamping circuit.
Referring to FIG. 1, there is provided a video signal input terminal 1 to which a video signal Sv is supplied. An amplifying circuit 2 might be formed of an operational amplifier or the like. An anode of a diode 3 is connected to the output terminal of the amplifying circuit 2. A power supply 4 is connected between the non-inverting terminal (+) of the amplifying circuit 2 and ground. An input coupling capacitor 5 is connected between an inverting input terminal (-) of the amplifying circuit 2 and the video signal input terminal 1. The cathode of the diode 3 is connected to the inverting input terminal of the amplifying circuit 2. A current source 6 is provided in order to process a discharge current of the input coupling capacitor 5. Operation of the sync chip clamping circuit will be described below with reference to the waveform diagram forming FIG. 2.
When the video signal Sv reaches the sync chip period T.sub.1, the voltage level at which the video signal Sv is held during this sync chip period T.sub.1 drops below the voltage Vc of the power supply 4 so that an output voltage Va of the amplifying circuit 2 rises and varies as shown in FIG. 2. When the output voltage Va of the amplifying circuit 2 reaches a voltage higher than the voltage of the video signal Sv, the diode 3 is turned on and the input coupling capacitor 5 is charged thereby to prevent the voltage at the inverting input terminal of the amplifying circuit 2 from becoming lower than the voltage Vc. In this way, the sync chip clamping circuit is operated so that the sync chip, which is held at the lowest potential of the video signal Sv, is brought to the voltage level equal to the voltage Vc of the power supply 4. An integrated circuit manufactured by a bipolar process is used in order to implement the sync chip clamping circuit shown in FIG. 1 as an integrated circuit.
Because a digital signal processing is increased and the integrated circuit must be formed as the large scale integrated circuit, it is customary that a video signal is processed by an integrated circuit manufactured by a CMOS (complementary metal oxide semiconductor). With this CMOS process, however, it is impossible to implement a diode just in the manner, for example, of the diode 3 shown in FIG. 1. Japanese Patent Publication No. 4-31473 describes such a sync chip clamping circuit in which an integrated circuit according to the CMOS process is realized without using a diode.
FIG. 3 is a diagram showing a sync chip clamping circuit made by the CMOS process as disclosed in Japanese Patent Publication No. 4-31473.
Referring to FIG. 3, an amplifying circuit 11 comprises a plurality of CMOS transistors Q.sub.3 through Q.sub.9 and corresponds to the amplifying circuit 2 shown in FIG. 1. There are provided inverters 12, 13. In particular, the inverter 13 comprises a pair of CMOS transistors Q.sub.2 and Q.sub.2 as shown in FIG. 3. There are provided resistors 14, 15. These resistors 14, 15 and the inverters 12, 13 correspond to the diode 3 shown in FIG. 1. The resistors 14, 15 and the inverters 12, 13 can realize a similar function to that of the diode 3 by selecting a resistance value of the resistor 15 to be smaller than a resistance value of the resistor 14.
Moreover, the amplifying circuit 11 includes a phase compensation capacitor 16 to stabilize operation of the sync chip clamping circuit. The phase compensation capacitor 16 has a large capacitance because the inverters 12, 13 having an amplifying action are connected to the rear stage of the amplifying circuit 11. A resistor 17 is connected to the capacitor 16 in series in order to prevent a response speed of the amplifying circuit 11 from being decreased even when the phase compensation capacitor 16 is formed of a capacitor having a large capacitance.
In this connection, with a prior art type of sync chip clamping/sync separation circuit according to the CMOS process such as described above, since the resistor 17 for phase compensation is required to have high accuracy, therefore the area of this resistor 17 becomes large, and, together with the increase of the capacitance of the capacitor 16 for phase compensation to a large value, this means that problems arise of an increase in the overall size of the circuit, as well as an increase in the cost thereof.